1. Field of the Invention
The present invention relates to an integrated circuit and, more specifically, to a method for forming interconnection levels of an integrated circuit.
2. Discussion of the Related Art
Integrated circuits are comprised of a large number of electronic components which are formed in and on a semiconductor wafer. To properly connect these components, several interconnection levels form the upper portion of the integrated circuits. Each interconnection level comprises conductive tracks. Vias are formed to connect conductive tracks of different interconnection levels.
FIG. 1 is a cross-section view of an example of the stack of several interconnection levels (Ni, Ni+1, Ni+2 . . . ) of an integrated circuit, level N1 being the interconnection level closest to the electronic components.
Each interconnection level Ni comprises a portion Mi in which are formed conductive tracks 10, located above a portion Vi in which are formed vias 12 of contact between tracks of adjacent levels (currently, the vias of interconnection level N1 are of a different nature than the vias of the other levels). In this drawing, the cross-section plane is such that the tracks are cut widthwise, so that conductive tracks 10 appear to be of same cross-section area as vias 12. Vias 12 enable properly connecting two conductive tracks 10 located in two neighboring interconnection levels. As an example, tracks 10 and vias 12 may be made of copper. A dielectric material 14 separates tracks 10 from one another and vias 12 from one another.
Nowadays, electronic components formed in integrated circuits operate at higher and higher frequencies. The frequency increase results in an increase in the values of the stray capacitances which form between the different conductive portions. Further, the continuous miniaturization of electronic components results in a decrease in the size of conductive tracks and a decrease in distances between tracks and between vias, which also increases the values of stray capacitances. Stray capacitances may disturb significantly the operation of a circuit. It is thus desired to decrease as much as possible such stray capacitances and, for this purpose, so-called “low-k” dielectric materials having very low relative permittivities, typically smaller than 3, are used between the different conductive portions.
However, the porosity of dielectric material 14 poses various problems. Especially, the copper of conductive tracks 10 diffuses more easily into porous dielectric materials than into non-porous dielectric materials. To limit such a diffusion, it is particularly useful to form, between two neighboring interconnection levels, a layer 16 which, conventionally, stops the diffusion of conductive material from an interconnection level to the dielectric material of the upper interconnection level and which forms an etch stop layer. Vias 12 cross layer 16. As an example, layer 16 may be made of silicon-carbon nitride (SiCN). It has also been provided to form a barrier layer (not shown) around the conductive tracks and the vias, this layer being made of a conductive material capable of avoiding the diffusion of the conductive material present in an interconnection level towards the porous dielectric material of the same interconnection level. This barrier layer is, for example, formed of tantalum and of tantalum nitride.
Further, on manufacturing of the stack of interconnection levels, various etch and/or polishing and cleaning operations are carried out in liquid or gas phase. Contaminating products may thus penetrate into the pores of the porous dielectric material during these operations. This may cause an alteration of the porous material or an increase in its relative permittivity, which limits the advantage of using such a porous material.
A way to restore the characteristics of the porous material comprises performing, after having formed each interconnection level, an anneal to eliminate the contaminating products present in the porous dielectric material.
FIG. 2 is a cross-section view illustrating a stack of two interconnection levels Ni and Ni+1. This drawing illustrates the result obtained after having carried out a chem./mech. polishing step (CMP) on the structure and an anneal step aiming at eliminating the contaminating products present in interconnection level Ni+1. The conductive tracks of the two interconnection levels are shown lengthwise in cross-section view.
Interconnection level Ni comprises conductive tracks 20 surrounded with a porous dielectric material 22. The bottom and the walls of conductive tracks 20 are covered with a thin barrier layer 24 of a material avoiding the diffusion of conductive material from conductive tracks 20 to porous dielectric material 22. A thin layer 26 of a material avoiding the diffusion of conductive material from conductive tracks 20 to interconnection level Ni+1, for example, made of SiCN, extends above interconnection level Ni. Interconnection level Ni+1, which comprises conductive tracks 28 connected by vias 30 to conductive tracks 20 of interconnection level Ni is formed above thin layer 26. A porous dielectric material 32 separates conductive tracks 28 from one another and vias 30 from one another. The walls and the bottom of conductive tracks 28 and of vias 30 are covered with a thin barrier layer 34 of a conductive material. Interconnection levels Ni and Ni+1 may be obtained by different known methods.
On forming of interconnection level Ni+1, the etch and/or polishing and cleaning steps cause the contamination of porous dielectric material 32. An additional step, where an anneal of the structure is performed to enable evaporation of the contaminants, is then carried out. As an example, this anneal step may be carried out at a temperature of approximately 300° C. for approximately 30 minutes. This anneal needs to be performed before deposition of a layer homologous to layer 26 which would create a barrier against the evaporation of contaminants.
In FIG. 2, arrows 36 illustrate the evacuation, during the anneal, of the contaminating products present in porous dielectric material 32. Although the anneal enables eliminating the contaminating products present in porous dielectric material 32, it should be noted that it also causes the expansion of the conductive material of conductive tracks 28. This expansion modifies the upper surface of conductive tracks 28 and makes it rough. Problems, for example, in terms of reliability, may then arise when another interconnection level is desired to be formed on the upper surface of interconnection level Ni+1. Further, since porous dielectric material 32 is not protected on its upper surface, it is contaminated again by the contact with the air, especially by water vapor, when the structure is taken out of the furnace in which the anneal has been performed. This recontamination is illustrated in FIG. 2 by arrows 38.
To limit the expansion of the conductive material, the anneal temperature may be decreased. However, a decrease in the anneal temperature causes an increase in the duration of this anneal and decreases its efficiency.